A 0.5p,m Pixel Frame-Transfer CCD Image Sensor in 110nm CMOS

and digital circuits. The FFT-CCD image sensor consists of a The first image sensor with submicron pixel pitch is reported. CCD pixel array, a CCD storage array, a horizontal CCD, and Test structures comprising 16 x 16 pixel Full-Frame-Transfer a source follower readout circuit (see Fig. 1). The pixel array (FFT) CCDs with 0.5,um pixels are fabricated in a single-poly uses no metal layers to achieve maximum light sensitivity, 110nm CMOS process. Characterization results demonstrate while the rest of the image sensor is light shielded by several charge transfer efficiency of 99.9%, QE of 48% at 550nm, metal layers that are also used to distribute global control conversion gain of 193,uV/e-, well capacity of 3550e-, dark signals. current of 50e-/sec with nonuniformity of 25%, peak SNR of The image sensor is designed and fabricated in a 110nm 28dB and dynamic range of 60dB. These performance metrics CMOS Image Sensor (CIS) process. Fig. 2 shows an SEM are within the range of consumer image sensors and suggest of the image sensor. Fig. 3 shows a 4 x4 section of the pixel that further reduction in pixel size is feasible. array and Fig. 4 shows SEM cross-sections in both directions. Each pixel consists of a single poly electrode, a channel, and Introduction a channel stop. The poly is N+ pattern doped with the S/D Pixel scaling in image sensors has aimed at increasing spatial implant masked out in between electrodes. No silicide is used resolution for a given optical format. As pixel size is approachin the pixel array area. STI is used as a channel stop in the ing the limits of conventional optics, the improvement in vertical direction. An SEM of the horizontal CCD with the resolution is diminishing. Scaling pixels beyond these limits, fill-and-spill input, the floating diffusion for charge to voltage however, can provide new imaging capabilities beyond merely conversion, and the reset gate are shown in Fig. 7. The reset attempting to increase resolution. In [1], we show that a multigate is N+ doped with channel implant for negative threshold aperture image sensor comprising a 2D array of apertures, voltage. each having its own optics and small submicron-pixel image The FFT-CCD performs snap shot imaging using global sensor, can simultaneously capture both a 2D image and a electronic shutter. The capture of a frame can occur sidepth map of the scene. We further argue that depth resolution multaneously with the read out of a previous frame. To improves with pixel scaling. The general idea is as follows. minimize pixel pitch, ripple transfer operation (as opposed to Each feature in the scene is captured by several apertures. the more common phased transfer) is used. An image can be Changing the depth of a feature causes displacements in their captured by integrating photocharge under each electrode or positions within the apertures. Depth can then be inferred from under every other electrode for interlaced operation. In either these displacements. As discussed in [1], displacements can be case, integration begins by depleting the CCDs of charge measured at higher resolution than the typical spot-size limit via transfer to the upper diffusion VO. During integration, of the objective lens. Deeply scaled pixels can also enable the pixel array electrodes are held at an intermediate voltage high resolution near-field imaging for such applications as Vstore. At the end of integration, the accumulated charge is microscopy and in vivo imaging [2]. ripple transferred row-by-row to the storage array (see Fig. 5). This paper presents the design and characterization of the The electrodes between the row of pixels to be read and their first submicron pixel image sensor. The reported 0.5,um pixel storage row are first set to a high voltage Vtransfer and then pitch is 3 times smaller than recently published CCD and the charge is shifted down one row at a time by sequentially CMOS image sensors [3], [4]. To characterize our design, applying a negative voltage Vsolate to each electrode. we fabricated test structures comprising arrays of 16 x 16, After transferring the charge from the pixel array to the 0.5,um pixel Full-Frame-Transfer (FFT) CCDs, each with frame buffer, the transfer through the horizontal CCD is source follower readout circuit, in 110nm single-poly CMOS. performed in even and odd phases. While the even columns We first discuss the design, fabrication, and operation of the are loaded into the horizontal CCD, it is essential to preserve image sensor, and then present simulation and characterization the charge in the odd columns. A simulation of this process results of the test structures. is shown in Fig. 6. The charge in the columns under V34 is shifted to V35 (steps 1 and 2 in the figure). The horizontal Design, Fabrication, and Operation electrodes are initially held at Vjsoiate to keep all charge We choose an FFT-CCD architecture to achieve both high under V35. Then, the even horizontal electrodes are brought optical coverage and large well capacity for deeply scaled to Vtransfer, which forces the even column charge to drain pixels and implement the image sensor in CMOS to enable into the horizontal CCD (step 3). Potential barriers between fast multi-aperture sensor readout and the integration of analog the even horizontal electrodes are enforced by holding the odd 1-4244-0439-X/07/$25.00 © 2007 IEEE 1003 Authorized licensed use limited to: Stanford University. Downloaded on March 02,2010 at 16:48:15 EST from IEEE Xplore. Restrictions apply. electrodes at Vsolate, while the STI region under the horizontal Conclusion electrodes (shown in the figure) provides the isolation along The first submicron pixel image sensor is reported. Characthe horizontal axis. Next, V34 is brought to Vstore and a partial terization results show promising performance. While dark transfer occurs at the odd columns from V35 to V34 (step current is comparable to that of 3T CMOS APS image sensors, 4). A full charge transfer is now forced in both directions it is higher than that of state-of-the-art 4T CMOS APS. This by slowly dropping V35 to Vsolate (step 5). This transfer is due to the storage and transfer of charge along the Si/SiO2 mechanism relies on the condition that the fringing field from interface. Lower dark current may be achievable using channel horizontal electrodes remain larger than that from V34. This and stop implants. While the crosstalk is acceptable at short condition is satisfied by bringing V34 up to Vstore at the wavelengths, process modifications such as the addition of a same time that V35 is dropping to Visolate. Once charge is graded epi region may help to improve it at long wavelengths. completely transfered to the horizontal CCD, V34 is set close to Vtransfer to ensure that all odd column charge is efficiently Acknowledgments passed backwards (step 6). Next, each charge in the horizontal The authors thank CH Tseng, David Yen, Chun-Yao Ko, JC CCD is ripple shifted to the floating diffusion node where it is Liu, Ming Li, and SG Wu from the CIS R&D group at TSMC buffered and double sampled using a source follower circuit. for fabrication. Keith is supported by a Hertz Foundation This procedure is repeated for the remaining charge in the odd Fellowship. columns confined by the V34 electrode. References Simulation and Measurement Results [1] K. Fife, A. El Gamal, and H.-S. P. Wong, "A 3D multi-aperture image sensor architecture," Custom Integrated Circuits Conference, pp. 281Simulated surface potentials along the channel under various 284, Sep. 2006. conditions are shown in Fig. 8. Applying Vstore = 0.5V [2] T. Massoud and S. Gambhir, "Molecular imaging in living subjects: creates potential barriers of 0.3V between electrodes, which Seeing fundamental biological processes in a new light," Genes & Dev, creates of bpp. 545-580, 2003. facilitates charge confinement under each electrode. During [3] M. Oda, T. Kaida, S. Izawa, T. Ogo, K. Itsumi, Y Okada, and K. Sasada, charge transfer, these barriers are overcome by applying "A 1/4.5in 3.1M pixel FT-CCD with 1.56,um pixel size for mobile Vtransfer = 1 .5V to the receiving electrode and Vsolate = -0-5V applications," ISSCC, pp. 346-348, Feb. 2005. [4] M. Cohen, F. Roy, D. Herault, Y. Cazaux, A. Gandolfi, J. Reynard et al., to the electrode with charge. While these barriers provide "Fully optimized Cu based process with dedicated cavity etch for 1.75,um single electrode confinement, the well capacity is limited to and 1.45,um pixel pitch CMOS imager sensors," IEDM, pp. 127-130, less than 500ebefore smear. Operation of the array using Dec. 2006. even and odd fields with Vsolate applied between the even/odd electrodes during integration increases the well capacity by .W nearly 10 fold. As such, this two-field approach is used in all reported measurements. We also simulated the amount I2.. of cross-talk between neighboring pixels due to drift and v3 .. Pixel diffusion in the bulk by inducing 500e-h pairs in the bulk * Array with transient analysis. Fig. 9 plots the electron density under V-6 ..I electrodes for charge induced at 0.5,um and 2.0,um, resulting V17 j in 85% and 20% collection at the intended center electrode, V18 respectively. These results show the need to improve cross-talk V19 ... at longer wavelengths. V20 . Frame Electrical characterization is performed by loading charge . Buffer patterns into the horizontal shift register through VP. The V34-l j conversion gain is obtained by measuring the variance of dark V35 shot noise on the floating diffusion. Charge transfer efficiency (CTE) is measured by moving charge packets through all the ] Transfer columns of the vertical array via the horizontal CCD. Noise TST from the fill-and-spill operation is removed by averaging and H 15 the total transfer times are kept short to eliminate corruption H14i from dark current. Fig. 10 plots measured charge versus the HOi number of transfers, which shows CTE of 99.9%. The results 1XSore l ........Source of optical characterization are given in Fig. 11-12. Note that j Follower despite the use of poly electrodes, the blue response is quite RS-........_ Readout acceptable. This is due to the thin the poly layer and the open }....CC L space in between each electrode. Table I provides measured . . ~~~~~~~~~Fig. 1. FFT-CCD image sensor schematic. Actual test structure size is sensor imaging characteristics. 16 x 16.